Packaging of power semiconductor dies of ever shrinking size and with ever reducing parasitic impedance has been driven by the consumer market on an ongoing basis. The following briefly reviews some related works.
FIG. 21 illustrates a prior art wherein two MOSFET semiconductor dies are packaged each with bond wires connected to its source and gate electrodes. While the associated assembly process is simple, the number of bond wires per package is limited by the package size owing to the significant size of wire bonding tools and technical constraints of the wire bonds—for example, bond wires should not cross each other. Additionally, the small cross section of bonding wires causes high connecting impedances (resistance and inductance) that in turn lower device current rating and can sometimes limit device operating frequency as well.
In U.S. Pat. No. 6,040,626 entitled “Semiconductor package” granted on Mar. 21, 2000 by Cheah et al, as illustrated in FIG. 22, clip bonding for source electrical connection was described. Semiconductor package 110 includes a bottom plate portion 13 and terminals 12a, 12b. The semiconductor package 110 also includes a housing 22 formed from a moldable material. A beam portion 34 is integrally formed into one flowing member which extends from one lateral edge of a plate portion 30 and terminates at terminals 12b. A metalized region 19 defines a gate of a MOSFET die 16. The semiconductor die 16 includes a metalized region 18 defining a connection area for a top surface of the semiconductor die 16. The metalized region 19 is electrically coupled to one terminal 12b via wire bond 20. Thus, U.S. Pat. No. 6,040,626 employs a mixed connection to the MOSFET die 16 top surface, namely, a low resistance plate portion 30 for connecting to the source and a wire bond 20 for connecting to the gate 19. A gate runner (or bus) 19a couples the gate metalized region 19 to the source areas of the surface of the die 16. It is preferred that the plate portion 30 extend laterally beyond outermost portions of the gate runner 19a. It is also preferable that the plate portion 30 extends beyond and cover as much of the gate runner 19a as possible. This ensures that improved performance is achieved. While clip bonding, owing to its much larger cross section, offers lower connecting impedances hence high current rating and possibly high device operating frequency as well, its application to small package sizes is difficult as two internal connections are required per clip and small clips are hard to handle, align and position during the packaging process.
In U.S. Pat. No. 6,689,642 entitled “Semiconductor device and manufacturing method thereof” granted on Feb. 10, 2004 by Fukuda, as illustrated in FIG. 23, a dual lead frame structure and assembly method for power MOSFET were described for reducing its on-state resistance and improving its production efficiency. The semiconductor package includes a lower frame 4 having a header 2 for fixing a semiconductor chip and corresponding external leads 3d, 3g, a semiconductor chip fixed on the header, an upper frame 7 having a connection electrode 6 fixed on a current passage electrode 5 formed on the top face of the semiconductor chip and the corresponding leads 3s, and a resin mold. This two-frame configuration provides extremely low on-state resistance and good production efficiency. The lower frame 4 itself is punched out from a copper material. The lower frame 4 includes a header 2 located in the center of the lower frame 4, three external leads 3d combined with the header 2 as one unit and extending from the header 2 to the outer frame 9, and an external lead 3g for another electrode with one end being close to the header 2 and another end being connected to the outer frame 9. Round index holes 12 are formed at both side edges of the outer frame 9 of the lower frame 4 with a constant interval for each side. These index holes are used for the positioning and the pitch-by-pitch transportation in the procedures of the manufacturing method. A square position-determining index hole for positioning the upper and lower frames 4, 7 is formed next to each round index hole 12 along the top side edge of the outer frame 9 of the lower frame. The round index holes 12 are formed at the locations corresponding to the lines connecting the centers of the headers 2 with a constant interval along the bottom side edge of the outer frame 9 of the lower frame 4. Two headers 2 and the corresponding external leads 3d are formed in one cell area 14 surrounded by the outer frame 9. The lower frame 4 has a 3.times.20 matrix of cell areas 14 between the top and bottom rows of index holes 12. Thus, one lower frame 4 has 60 cell areas and 120 headers 2 for fixing the semiconductor chips. The semiconductor chips are then fixed on each of the headers 2 in the cell areas 14 of the lower frame 4 by die bonding. That is, the semiconductor chips, such as power MOSFET bare chips, are fixed on the headers 2 of the lower frame 4 through the pre-form made of solder or silver paste using a die bonding instrument. During this procedure, the index holes 12 in the top and bottom side edges are used for the positioning of the headers 2 and for transporting the lower frame 4 by one pitch at a time. At the end, all the headers 2 of the lower frame 4 have a semiconductor chip fixed on themselves. Round index holes 12 are also formed at both side edges of the outer frame 9 of the upper frame 7 with a constant interval for each side, as in the case with the lower frame 4. These index holes are used for the positioning and the pitch-by-pitch transportation in the manufacturing method. A square position-determining index hole for positioning the upper and lower frames 4, 7 is formed next to each round index hole 12 along the top side edge of the outer frame 9 of the upper frame 7. The two position-determining index holes have an identical size and shape. Two connection electrodes 6 and the corresponding external leads 3s are formed in one cell area 14 surrounded by the outer frame 9. While the dual lead frame structure also offers high device current rating and lower connecting impedances, it entails a complicated assembly process. The assembly process either requires special machinery, or manual assembly, which greatly increases the cost and/or reduces the throughput.
U.S. application Ser. No. 11/799,467 disclosed a semiconductor package having dimpled plate interconnections. A source plate includes a plurality of dimples formed thereon. The dimples are concave with respect to a top surface of the source plate and include a through hole having an opening formed beyond a plane of a bottom surface thereof. Similarly, a gate plate includes a dimple that is concave with respect to a top surface of the gate plate and includes a through hole.
In US Patent Application 20080087992 entitled “Semiconductor package having a bridged plate interconnection” by Shi Lei et al, hereafter referred to as US 20080087992, a semiconductor package with a bridged source plate interconnection is disclosed for packaging a semiconductor die. A semiconductor package is illustrated that includes a leadframe having a die pad, a source contact portion and a gate contact portion. A bridged source plate includes a metal plate stamped or punched to form a bridge portion, valley portions on either side of the bridge portion, plane portions on either side of the valley portions and the bridge portion, and a connection portion depending from one of the plane portions.
In a commonly assigned U.S. patent application Ser. No. 12/130,663 with filing date May 30, 2008 and entitled “CONDUCTIVE CLIP FOR SEMICONDUCTOR DEVICE PACKAGE” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/130,663, a semiconductor device package with a conductive clip having separate parallel conductive fingers electrically connected to each other by conductive bridges is disclosed. A semiconductor device package is illustrated with its gate bond wire replaced with a gate clip. The device package includes a fused lead frame, a MOS device having top source, top gate and bottom drain located on top of the lead frame and a clip having separate parallel conductive fingers electrically connected to each other by conductive bridges. The clip is electrically bonded to the top source of the MOS device only at the bridges.
In a commonly assigned U.S. patent application Ser. No. 12/237,953 with filing date Sep. 24, 2008 and entitled “Top Exposed Clip with Window Array” by Shi Lei et al, hereafter referred to as U.S. application Ser. No. 12/237,953, a semiconductor device package with single stage clips is disclosed. Each single stage clip includes a metal sheet having arrays of windows thereon. The semiconductor device package includes a fused lead frame and a semiconductor device having contact regions on top and bottom surfaces. The semiconductor device may be a vertical metal oxide semiconductor (MOS) device having a top source contact, a top gate contact and a bottom drain contact. The semiconductor device is located on top of the lead frame with the bottom drain contact facing and making electrical contact with the main portion of the lead frame. The lead frame may be fused or non-fused. As an embodiment of U.S. application Ser. No. 12/237,953, the semiconductor device package includes single stage clips, which include two separate metal sheets having arrays of windows respectively.
In a commonly assigned U.S. patent application Ser. No. 12/326,065 entitled “Top-side Cooled Semiconductor Package with Stacked Interconnection Plates and Method” by Kai Liu et al, hereafter referred to as U.S. application Ser. No. 12/326,065, a top-side cooled semiconductor package with stacked interconnection plate is disclosed that includes a circuit substrate with terminal leads, a semiconductor die atop the circuit substrate, a low thermal resistance intimate interconnection plate for bonding and interconnecting a top contact area of the semiconductor die with the circuit substrate, a low thermal resistance stacked interconnection plate atop the intimate interconnection plate for top-side cooling, a molding encapsulant for encapsulating the package except for exposing a top surface of the stacked interconnection plate to maintain effective top-side cooling. The top portion of the stacked interconnection plate can include a peripheral overhang above the intimate interconnection plate. The peripheral overhang allows for a maximized exposed top surface area for heat dissipation independent of otherwise areal constraints applicable to the intimate interconnection plate. The stacked interconnection plate can be partially etched or three dimensionally formed to create the peripheral overhang.
In review of the above related works and the ongoing market demand of packaging power semiconductor dies with ever shrinking size and ever reducing parasitic impedance, it is desirable to further improve the fabrication and assembly process for packaging power semiconductor dies using interconnection plates.